Teradyne, Inc.

Filed a patent for "electrical isolation circuitry" on Thu, February 27, 2025

Filed a patent for "circuit board having an edge containing conductive regions" on Thu, February 20, 2025

Filed a patent for "generating a test program" on Thu, December 26, 2024

Filed a patent for "test systems configured to test devices at different temperatures" on Thu, November 21, 2024

Filed a patent for "controlling storage of test data based on prior test program execution" on Thu, September 26, 2024

Filed a patent for "identifying failures in device cores" on Thu, September 26, 2024

Filed a patent for "cable assembly containing self-calibration data" on Thu, August 15, 2024

Filed a patent for "test system that converts command syntaxes" on Thu, July 18, 2024

Filed a patent for "determining a correlation between power disturbances and data erors in a test system" on Thu, June 13, 2024

Filed a patent for "flattening a circuit board assembly using vacuum pressure" on Thu, November 23, 2023

Filed a patent for "method for reduction of sic mosfet gate voltage glitches" on Thu, December 21, 2023